TSM...the modular rail mount system
TSM - ARM/CPU
- 32bit processor S3C4530 with ARM7TDMI core, cache, DMA, HDLC (Bitbus), 2 32bit timers, 2 ser. interfaces with Rx and Tx FIFOs, I²C and Ethernet controller
- 4MByte flash-EPROM, 2 MByte RAM with 32bit-data-bus
- 512K flash (sectored) allowing updates of operating system mCAT2 realtime core with “Express-I/O” for convenient I/O access
- RAM battery backed-up
- Realtime clock with calendar
- Two RS232 interfaces
- 1 isolated RS485 network interface (BITBUS)
- Relays (change over switch) 1A/30V
- Configuration switch 0..F
- Optional: CAN interface
Process I/O:
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8 digital inputs 24V, optoisolated; optional use of two as event counters
- 8 digital outputs 24V, 1,5A, optoisolated and overload protected
- 8 analog inputs 10 bit; optionally 0..5V, 0..20mA or for Si-temperature-sensors (KTY)
- 2 analog outputs 8 bit; 0..5V
First Ethernet-CPU by ELZET80 and first CPU with ARM processor - the new standard in embedded computing. Ethernet joins traditional IT and control engineering: on one hand the built-in web server opens control tasks to the office world, on the other hand I/O functions can directly be called with nodeAccess™ on the TSM-ARMCPU.
Programmierung
The ARM-CPU is programmed in C based on the ported mCAT2-realtime-core that we are already using with our TLCS900 products. mCAT offers time or event based communication via messages between different tasks or between interrupt drivers and tasks. The hardware abstraction layer,“Express-I/O”, enables access to I/O with assigned names to any analog and digital inputs and outputs.
